(a) The gate that gives a 'low' output only when both its input are low. is an OR gate
The required design is as follows.
| Input | | Output |
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
(b) The Bate that gives a high output only when both the inputs are high is an AND gate.
The required design is as follows :
The'truth table' is as follows.
| Input | | Output |
| A | B | Y |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |